 |
 |
|
|
| |
 DDR2
240pin DIMM |
| |
|
Capacity
|
Chip Configuration |
Volt.
|
Speed |
|
Non-ECC With ECC
|
|
256MB
|
32M*16Bit (x4)
|
32M*16Bit (x5)
|
1.8 V
|
PC400;PC533;PC667 |
|
512MB
|
64M*8Bit (x8)
|
64M*8bit (x9)
|
1.8 V
|
PC400;PC533;PC667 |
|
1GB
|
16M*8Bit
(x16)
|
64M*8bit (x18)
|
1.8 V
|
PC400;PC533;PC667 |
|
2GB
|
128M*8Bit (x16)
|
128M*8bit (x18)
|
1.8 V
|
PC400;PC533;PC667 |
|
| |
|
| |
產品規格： |
|
|
|
˙ |
Package:FBGA |
|
˙ |
Double Data Rate architecture |
|
˙ |
JEDEC Standard |
|
˙ |
MRS
cycle with address key programs |
| |
*CAS latency: 3,4&5 |
| |
*Burst length: 4 & 8 |
| |
*Burst type: Nibble Sequential & Interleave |
|
˙ |
2 variations of refresh: Auto refresh & Self
refresh |
|
˙ |
Differential Data Stroge (DQS) |
|
˙ |
Differential clock inputs (CK and /CK) |
|
˙ |
Edge aligned data output, center aligned
data input |
|
˙ |
2 banks to be operated simultaneously or
independently |
|
˙ |
Serial Presence Detech with EEPROM |
|
|
|
|
|
DDR
184pin DIMM |
|
|
Capacity
|
Chip Configuration |
Volt.
|
Speed |
|
Non-ECC With ECC
|
|
128MB
|
16M*16Bit (x4)
|
|
2.6 V
|
PC133;PC166;PC200 |
|
256MB
|
32M*8Bit (x8)
|
32M*8bit (x9)
|
2.6 V
|
PC133;PC166;PC200 |
|
512MB
|
32M*8Bit
(x16)
|
32M*8bit (x18)
|
2.6 V
|
PC133;PC166;PC200 |
|
1GB
|
64M*8Bit (x16)
|
64M*8bit (x18)
|
2.6 V
|
PC133;PC166;PC200 |
|
|
|
|
產品規格： |
|
|
˙ |
Package:TSOP |
|
˙ |
Double Data Rate architecture |
|
˙ |
MRS cycle with address key programs |
|
|
*CAS latency: CL2, 2.5 & 3 |
|
|
*Burst length: 2, 4 & 8 |
|
|
*Burst type: Sequential & Interleave |
|
˙ |
2 variations of refresh: Auto refresh & Self
refresh |
|
˙ |
2 Banks to be operated simultaneously or
independently |
|
˙ |
Serial Presence Detect support |
|
|
|
| |
|
